Field of the Invention
Embodiments of the present invention relate generally to integrated circuit chip packaging and, more specifically, improved package final planarity.
Description of the Related Art
In the packaging of integrated circuit (IC) chips, a semiconductor chip is usually mounted on a packaging substrate to facilitate electrical connection of the chip to a motherboard or other printed circuit board (PCB). ICs release heat as a result of power consumption. The heating up of the IC can adversely affect the power, performance and reliability of the device. The thermal concerns for ICs are nothing new and typically addressed during a product design. However, increased miniaturization of components and package density of the ICs have led to a decrease in available real-estate on the package to address the thermal concerns.
As an IC chip package heats up, the package can warp. Warping can break solder joints and terminal connections. Warping can damage an IC chip package beyond use or repair. The problem of warping has led to the inclusion of heat transfer and other microstructures for IC chip packaging. Examples of some of these microstructures include heat sinks and stiffing rings.
In order to provide the high density of electrical connections typical of modern IC chips and expanded wiring layout required for such chips, packaging substrates have advanced from being single-layered boards to multiple-layered boards that include multiple buildup layers formed on a core board. The microstructures used to address warping on these multiple-layered boards are typically located on the chip mounting surface of the packaging substrate. One such packaging substrate is illustrated in FIG. 1.
FIG. 1 provides a schematic cross-sectional view of a conventional packaged semiconductor device 180 configured to typical industrial practices. The packaged semiconductor device 180 includes an integrated circuit (IC) chip 107 coupled to a packaging substrate 100. The packaging substrate 100 provides the packaged semiconductor device 180 with structural rigidity as well as an electrical interface for routing input and output signals and power between the one or more IC chips 107 and an underlying support structure, such as a printed circuit board (PCB) (not shown). The one or more IC chips 107 may include any IC chip or die known in the art or later developed, such as a central processing unit, a graphics processing unit, or a memory chip, among others.
The packaging substrate 100 includes a substrate structure 125 having a stiffening microstructure 150 coupled thereto. The substrate structure 125 incorporates a core layer 101 and multiple buildup layers 102 on each side of the core layer 101. The core layer 101 may be fabricated from silicon, doped silicon such as n- or p-silicon, a carbon composite, or other suitable material. Buildup layers 102 may be fabricated from one or more conductive layers, such as copper layers, and one or more dielectric layers.
The stiffening microstructure 150 provides tensional rigidity to the packaging substrate 100 to promote planarity. In a conventional packaging substrate 100, the stiffening microstructure 150 is fastened to a chip mounting surface 110 of the substrate structure 125.
The stiffening microstructure 150 of the packaging substrate 100 may include a lid 151 (shown in phantom). The lid 151 may be fashioned from materials that provide certain thermal dynamic properties which may allow heat to more readily dissipate from the packaging substrate 100 and/or IC chip 107. The stiffening microstructure 150 may be adhered to the substrate structure 125 in a number of ways. Electrical and thermodynamic properties dictate the method and materials utilized in the adherence of the stiffening microstructure 150 to the substrate structure 125. For instance, the stiffening microstructure 150 may be coupled to the chip mounting surface 110 of the substrate structure 125 using a bonding agent (i.e., an adhesive) with properties selected to promote heat transfer in order to remove heat from the packaging substrate 100. Furthermore, the stiffening microstructure 150 provides tensional rigidity to the packaging substrate 100 to promote coplanarity with the IC chip 107 and underlying PCB (not shown).
A plurality of micro-bumps 103 are arrayed on the chip mounting surface 110 of the packaging substrate 100 and a plurality of solder balls 104 are arrayed on a bottom surface 120 for PCB mounting. The IC chip 107 is electrically coupled to chip mounting surface packaging substrate 100 by the micro-bumps 103, and packaging substrate 100 is electrically coupled to a support structure, such as a PCB (not shown), with the solder balls 104. To form electrical interconnects between micro-bumps 103 and solder balls 104, via structures 130 and interconnect lines 140 defining conductive pathways 164 are formed in core layer 101 and buildup layers 102. Solder mask layers 105 are utilized to prevent electrical short circuit connections between the solder balls 104 and micro-bumps 103 and the conductive pathways 164 formed through the substrate structure 125.
As shown in FIG. 1, a stiffening microstructure 150 is positioned along the on the chip mounting surface 110 of packaging substrate 100. The stiffening microstructure 150 may be configured as a ring 152 or a lid 151 (shown in phantom) to provide torsional stiffness to the packaging substrate 100 so as to resists warping. The lid microstructure 151 may act as a heat sink as well for the packaging substrate 100.
As more and more devices are added to the packaging substrate 100, connection lengths are minimized further and substrate structures 125 are thinned, thereby reducing the rigidity of the substrate structures 125. The thinned substrate structures 125 are more suspectible to stress due to heat and heat induced warping, which undesirably reduces the reliability of the packaged semiconductor device 180.
As the foregoing illustrates, there is a need in the art for a reliable packaging substrate that is easily manufactured and resist warping.